al4ca01/02/03/04/05 512/ 1k/ 2k/ 4k/ 8k x 9 asynchronous fifos applications - atm switches - routers - cable modems - wireless base stations - sonet(synchronous optical network) multiplexers - multimedia systems - tbc(time base corr ector) - hard disk cache memory - buffer for communications description th e al4ca01/02/03/04/05 asynchronous fifo (first in first out) memory provides completely independent 9bit bus width input and output port control that have a maximum data access time as fast as 12 ns. the products are available in densities from 4kbit to 64 kbit with word depths from 512bit to 8kbit. ordering information part number al4ca01, AL4CA02, al4ca03, al4ca04, al4ca05 package 32 - pin plastic plcc power supply +3.3v 10% plcc top view al4ca0 x x - xx - xx xxxx xxxxx averlogic 13 30 4 29 1 5 21 20 14 features high performance, low - power, fifo(first - in first - out) memory 512 x9 bit i/o port (al4ca01) 1k x9 bit i/o port (AL4CA02) 2k x9 bit i/o port (al4ca03) 4k x9 bit i/o port (al4ca0 4) 8k x9 bit i/o port (al4ca05) asynchronous 1 2 ns access time fully independent input/output port access empty, full, half full flags auto retransmit cascadable expansion in depth and width 3.3 - volt power tolerant of 5 - volt input standard 32 - pin plcc,
a ver l ogic t echnologies , i nc . tel : 1 408 361 - 0 400 e - mail: sales@averlogic.com url: www.averlogic.com december 14, 2001 the read and write operations are inter nally sequential through the managing of address pointers, with no address line control required to store and retrieve data. data is toggled in and out of the fifo through the use of the write and read enable pins. additional features of the al4ca0x seri es include: retransmit(/rt) that allows for reset of the read pointer and do the retransmit operation; empty, full and half - full flags can indicate the fifo accessible capacity. al4ca0x fifo memory is averlogic technologies, latest products that is desig ned to buffer data for a wide range of application such as optical storage controllers, networking switches and various communication applications. the embedded memory array with built - in address decoder, pointer manager and state - of - the - art circuits provi de an easy - to - use interface to serial read/write memory and offer a flexible way to manage memory in the system design. there are 3 flag signals, empty flag/output ready and full flag/input ready, and half full flags that enable further manipulation of the synchronous control. multiple al4cx0xs can be cascaded to expand the storage depth or can be used in parallel to expand bus width. the fifos are 3.3 - volt devices with 5 - volt input tolerance. and are available in the 32 - pin pl cc package. d istributed by : memory array 512 x9, 1k x9, 2k x9, 4k x9, 8k x9, 16k x9, input buffer output buffer write control logic read control logic flag logic expansion logic write pointer read pointer offset regissers reset logic input data bus output data bus /w /rs /r /ff /ef /xo /xi(/hf) al4ca0x fifo block diagram /fl(rt/)
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